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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78P083
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78P083 is a member of the PD78083 subseries of the 78K/0 series products. It includes an on-chip, 24-Kbyte, one-time PROM or EPROM. Because this device can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time-to-market of a new product. Caution The PD78P083DU does not maintain planned reliability when used in your systems' mass-produced products. Please use only experimentally or for evaluation purposes during trial manufacture.
The details of functions are described in the user's manuals. Be sure to read the following manuals before designing. PD78083 Subseries User's Manual 78K/0 Series User's Manual -- Instructions : IEU-1407 : IEU-1372
FEATURES
* Pin-compatible with mask ROM version (except VPP pin) * Internal PROM: 24 Kbytes Note * PD78P083DU: Reprogrammable (ideally suited for system evaluation) * PD78P083CU, PD78P083GB: One-time programmable (ideally suited for small-scale production) * Internal high-speed RAM: 512 bytes Note * Can be operated in the same supply voltage as the mask ROM version (VDD = 1.8 to 5.5 V) * Corresponding to QTOPTM Microcontrollers Note The internal PROM and internal high-speed RAM capacities can be changed by setting the internal memory size switching register (IMS). Remark QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM and are totally supported by NEC's programming service (from programming to marking, screening and verification).
*
Differs from the mask ROM version in the following points The same memory mapping as the mask ROM version is enabled by setting the internal memory size switching register (IMS).
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U11006EJ1V0DS00 (1st edition) (Previous No. IP-3556) Date Published June 1996 P Printed in Japan
The mark
*
shows major revised points.
(c)
1995
PD78P083
ORDERING INFORMATION
Part Number PD78P083CU PD78P083GB-3B4 PD78P083GB-3BS-MTX PD78P083DU 42-pin 44-pin 44-pin 42-pin Package plastic shrink DIP (600 mil) plastic QFP (10 x 10 mm) plastic QFP (10 x 10 mm) ceramic shrink DIP Internal ROM One-Time PROM One-Time PROM One-Time PROM EPROM
*
(with window) (600 mil) Caution
PD78P083GB has two kinds of package. (Refer to 9. PACKAGE DRAWINGS). Please refer an
NEC's sales representative for the available package.
QUALITY GRADE
Part Number PD78P083CU PD78P083GB-3B4 PD78P083GB-3BS-MTX PD78P083DU Package 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm) 44-pin plastic QFP (10 x 10 mm) 42-pin ceramic shrink DIP (with window) (600 mil) Quality Grades Standard Standard Standard Not applicable
Please refer to "Quality grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
PD78P083
78K/0 SERIES DEVELOPMENT
The following shows the 78K/0 series products development. Subseries names are shown inside frames.
Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin PD78078 PD78070A PD78058F PD78054 PD78018F PD78014 PD780001 PD78002 PD78083 PD78002Y PD78078Y PD78070AY PD78058FY PD78054Y PD78018FY PD78014Y A timer was added to the PD78054 and external interface function was enhanced ROM-less versions of the PD78078 EMI noise reduced product of the PD78054 UART and D/A converter were added to the PD78014 and I/O was enhanced Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities are available. An A/D converter and 16-bit timer were added to the PD78002 An A/D converter was added to the PD78002 Basic subseries for control On-chip UART, capable of operating at a low voltage (1.8 V)
FIPTM drive 100-pin 78K/0 Series 80-pin 64-pin PD780208 PD78044A PD78024 The I/O and FIP C/D of the PD78044A were enhanced. Display output total: 53 A 6-bit U/D counter was added to the PD78024. Display output total: 34 Basic subseries for driving FIP. Display output total: 26
LCD drive 100-pin 100-pin 100-pin PD780308 PD78064B PD78064 PD78064Y PD780308Y The enhanced SIO to the PD78064 and increased ROM and RAM capacities EMI noise reduced product of the PD78064 Subseries for driving LCDs, On-chip UART
IEBusTM supported 80-pin PD78098 The IEBus controller was added to the PD78054
LV control 64-pin PD78P0914 On-chip PWM, LV digital code decoder, and Hsync counter
3
PD78P083
The following table shows the differences among subseries functions.
Function Part Number Control PD78078 PD78070A ROM Capacity Timer 8-bit 8-bit D/A 2ch 3ch (UART: 1ch) 88 61 69 2.0 V - 2ch 53 1.8 V 2.7 V - - 1ch - 1ch 1ch 1ch - 8ch 8ch - 1ch 39 53 1ch (UART: 1ch) 33 2ch 74 68 54 1ch 1ch 1ch 8ch - 3ch (UART: 1ch) 57 2ch (UART: 1ch) 1.8 V 2.0 V - 1.8 V 2.7 V - Available - - Serial Interface I/O VDD MIN. External Value 1.8 V 2.7 V Expansion Available
8-bit 16-bit Watch WDT A/D 1ch 1ch 1ch 8ch
32 K to 60 K 4ch -
PD78058F 48 K to 60 K 2ch PD78054 16 K to 60 K
PD78018F 8 K to 60 K PD78014 8 K to 32 K
PD780001 8 K PD78002 PD78083 FIP drive PD780208 32 K to 60 K 2ch PD78044A 16 K to 40 K PD78024 LCD drive 24 K to 32 K 8 K to 16 K
PD780308 48 K to 60 K 2ch PD78064B 32 K PD78064 16 K to 32 K 32 K to 60 K 2ch
IEBus supported LV control
PD78098
1ch
1ch
1ch
8ch
2ch
3ch (UART: 1ch) 69
2.7 V
Available
PD78P0914 32 K
6ch
-
-
1ch
8ch
-
2ch
54
4.5 V
Available
4
PD78P083
FUNCTION DESCRIPTION
Item Internal memory Function * PROM: 24 Kbytes * RAM Internal high-speed RAM: 512 bytes Memory space General register Instruction cycles Instruction set 64 Kbytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Instruction execution time variable function is integrated. 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@5.0-MHz operation with main system clock) * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, Boolean operation) * BCD adjust, etc. I/O ports Total * CMOS input * CMOS input/output A/D converter Serial interface Timer Timer output Clock output Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt Power supply voltage Operating ambient temperature Packages : 33 :1 : 32
Note Note
* 8-bit resolution x 8 channels * 3-wire serial I/O/UART mode selectable: 1 channel * 8-bit timer/event counter: 2 channels * Watchdog timer: 1 channel 2 pins (8-bit PWM output enable) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock) 1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz (@ 5.0-MHz operation with main system clock) Internal Internal Internal : : : 8 1 1 external : 3
VDD = 1.8 to 5.5 V TA = -40 to +85C * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm) * 42-pin ceramic shrink DIP (with window) (600 mil)
Note
Internal PROM and high-speed RAM capacities can be changed by setting the internal memory size switching register (IMS).
5
PD78P083
PIN CONFIGURATIONS (Top View) (1) Normal operating mode * 42-pin plastic shrink DIP (600 mil) PD78P083CU * 42-pin ceramic shrink DIP (with window) (600 mil) PD78P083DU
P55 P56 P57 P30 P31 P32 P33 P34 P35/PCL P36/BUZ P37 P00 P01/INTP1 P02/INTP2 P03/INTP3 RESET VPP X2 X1 VDD AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS P54 P53 P52 P51 P50 P100/TI5/TO5 P101/TI6/TO6 P70/RXD/SI2 P71/TXD/SO2 P72/ASCK/SCK2 P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS AVREF
Cautions 1. 2. 3.
Connect VPP pin directly to VSS. Connect AVDD pin to VDD. Connect AVSS pin to VSS.
6
PD78P083
* 44-pin plastic QFP (10 x 10 mm) PD78P083GB-3B4, PD78P083GB-3BS-MTX
P11/ANI1
P10/ANI0
AVSS
RESET
AVREF
AVDD
VDD
VPP
P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 P72/ASCK/SCK2 P71/TXD/SO2 P70/RXD/SI2 P101/TI6/TO6 P100/TI5/TO5
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
NC
X1
X2
P03/INTP3 P02/INTP2 P01/INTP1 P00 P37 P36/BUZ P35/PCL P34 P33 P32 NC
10
11 23 12 13 14 15 16 17 18 19 20 21 22
P50
P51
P52
P53
P54
P55
P56
P57
P30
Cautions 1. 2. 3. 4.
Connect Connect Connect Connect
VPP pin directly to VSS. AVDD pin to VDD. AVSS pin to VSS. NC pin to VSS for noise protection (It can be left open).
P31
VSS
7
PD78P083
P00 to P03 P10 to P17 P30 to P37 P50 to P57 P70 to P72 P100, P101 INTP1 to INTP3 TI5, TI6 TO5, TO6 SI2 SO2 SCK2 RxD TxD ASCK
: Port 0 : Port 1 : : : : : : : : : : : : Port Port Port Port 3 5 7 10
PCL BUZ X1, X2 RESET ANI0-ANI7 AVDD AVSS AVREF VDD VPP VSS NC
: Programmable Clock : Buzzer Clock : : : : : : : : Crystal (Main System Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Programming Power Supply
Interrupt from Peripherals Timer Input Timer Output Serial Input Serial Output Serial Clock Receive Data Transmit Data
: Ground : Non-connection
: Asynchronous Serial Clock
8
PD78P083
(2) PROM programming mode * 42-pin plastic shrink DIP (600 mil) PD78P083CU * 42-pin ceramic shrink DIP (with window) (600 mil) PD78P083DU
A5 A6 A7 OE CE PGM A8 (L) A9 (L) RESET VPP Open (L) VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS A4 A3 A2 A1 A0 A10 A11 A12 A13 A14 D7 D6 D5 D4 D3 D2 D1 D0 VSS VSS
Cautions 1. 2. 3. 4.
(L):
Individually connect to VSS via a pull-down resistor.
VSS: Connect to GND. RESET: Set to low level. Open: Leave open.
9
PD78P083
* 44-pin plastic QFP (10 x 10 mm) PD78P083GB-3B4, PD78P083GB-3BS-MTX
VSS
D1
D0
(L)
RESET
Open
VDD
VDD
VSS
VPP
D2 D3 D4 D5 D6 D7 A14 A13 A12 A11 A10
1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26 25 24
A9
A8 PGM (L)
10
11 23 12 13 14 15 16 17 18 19 20 21 22
Cautions 1. 2. 3. 4. A0 to A14 D0 to D7 CE OE PGM
(L): Individually connect to VSS via a pull-down resistor. VSS: Connect to GND. RESET: Set to low level. Open: Leave open. RESET VDD VPP VSS : Reset : Power Supply : Programming Power Supply : Ground
: Address Bus : Data Bus : Chip Enable : Output Enable : Program
10
VSS
OE
CE
A0
A1
A2
A3
A4
A5
A6
A7

44 43 42 41 40 39 38 37 36 35 34 33
(L)
(L)
(L)
PD78P083
BLOCK DIAGRAM
P00 P100/TI5/TO5 8-bit TIMER/ EVENT COUNTER 5 PORT 0 P01-P03
P101/TI6/TO6
8-bit TIMER/ EVENT COUNTER 6 WATCHDOG TIMER 78K/0 CPU CORE
PORT 1
P10-P17
PROM (24 KBytes)
PORT 3
P30-P37
SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP1/P01INTP3/P03
SERIAL INTERFACE 2
PORT 5
P50-P57
A/D CONVERTER DATA MEMORY (512 Bytes)
PORT 7
P70-P72
INTERRUPT CONTROL BUZZER OUTPUT
PORT 10
P100, P101
BUZ/P36
RESET SYSTEM CONTROL X1 X2
PCL/P35
CLOCK OUTPUT CONTROL
VDD
VSS
VPP
11
PD78P083
CONTENTS
1. 2.
DIFFERENCES BETWEEN THE PD78P083 AND MASK ROM VERSIONS *** 13 PIN FUNCTIONS *** 14
2.1 2.2 2.3 Pins in Normal Operating Mode *** 14 Pins in PROM Programming Mode *** 16 Pin Input/Output Circuits and Recommended Connection of Unused Pins *** 16
3. 4.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) *** 18 PROM PROGRAMMING *** 19
4.1 4.2 4.3 Operating Modes *** 19 PROM Write Procedure *** 21 PROM Read Procedure *** 25
5. 6. 7.
PROGRAM ERASURE (PD78P083DU ONLY) *** 26 OPAQUE FILM ON ERASURE WINDOW (PD78P083DU ONLY) *** 26 ONE-TIME PROM VERSION SCREENING *** 26 ELECTRICAL SPECIFICATIONS *** 27 PACKAGE DRAWINGS *** 45
* *
8. 9.
10. RECOMMENDED SOLDERING CONDITIONS *** 49 APPENDIX A. APPENDIX B. DEVELOPMENT TOOLS *** 50 RELATED DOCUMENTS *** 52
12
PD78P083
1. DIFFERENCES BETWEEN THE PD78P083 AND MASK ROM VERSIONS
The PD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which has program write, erasure and rewrite capability. Setting the internal memory size switching register (IMS) makes the functions except the PROM specification identical to the mask ROM versions, that is, the PD78081 and PD78082. Differences between the PD78P083 and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences between the PD78P083 and Mask ROM Versions
Parameter ROM type ROM capacity Internal high-speed RAM capacity Internal ROM and internal high-speed RAM capacity change by internal memory size switching register IC pin VPP pin Electrical specifications No Yes Refer to a data sheet of each product Yes No 24 Kbytes 512 bytes Can be changed
Note
PD78P083 One-time PROM/EPROM
Mask ROM Versions Mask ROM PD78081 : PD78082 : PD78081 : PD78082 : 8 Kbytes 16 Kbytes 256 bytes 384 bytes
Can not be changed
Note
The internal PROM becomes 24 Kbytes and the internal expansion RAM becomes 512 bytes by the RESET input.
13
PD78P083
2. PIN FUNCTIONS
2.1 Pins in Normal Operating Mode
(1) Port pins
Pin Name P00 P01 P02 P03 Input/Output Input Input/output Port 0 4-bit input/output port Function Input only Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P10-P17 Input/output Port 1 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P30-P34 P35 P36 P37 P50-P57 Input/output Input/output Port 3 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. Port 5 8-bit input/output port Can drive up to seven LEDs directly. Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P70 P71 P72 Input/output Port 7 3-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P100 P101 Input/output Port 10 2-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. Input TI5/TO5 TI6/TO6 Input SI2/RxD SO2/TxD SCK2/ASCK Input --
Note
After Reset Input Input
Alternate Function -- INTP1 INTP2 INTP3
Input
ANI0-ANI7
Input PCL BUZ
--
--
Note
When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode. The on-chip pull-up resistor is automatically disabled.
14
PD78P083
(2) Non-port pins
Pin Name INTP1 INTP2 INTP3 SI2 SO2 SCK2 RxD TxD ASCK TI5 TI6 TO5 TO6 PCL BUZ ANI0-ANI7 AVREF AVDD AVSS RESET X1 X2 VDD VPP VSS NC Input Input - - - - - Positive power supply. High-voltage applied during program write/verification. Connected directly to VSS in normal operating mode. Ground potential. Does not internally connected. Connect to VSS. (It can be left open) - - - - Output Output Input Input - - Clock output. (for main system clock trimming) Buzzer output. A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply. Connected to VDD. A/D converter ground potential. Connected to VSS. System reset input. Main system clock oscillation crystal connection. Input Input Input - - - - - - - - Output Input Output Input/Output Input Output Input Input Serial interface serial data input. Serial interface serial data output. Serial interface serial clock input/output. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input to 8-bit timer (TM5). External count clock input to 8-bit timer (TM6). 8-bit timer output. Input Input Input Input Input Input Input Input Input/Output Input Function External interrupt input by which the active edge (rising edge, falling edge, or both rising and falling edges) can be specified. After Reset Input Alternate Function P01 P02 P03 P70/RxD P71/TxD P72/ASCK P70/SI2 P71/SO2 P72/SCK2 P100/TO5 P101/TO6 P100/TI5 P101/TI6 P35 P36 P10-P17 - - - - - - - -
15
PD78P083
2.2
Pins in PROM Programming Mode
Input/Output Input Function PROM programming mode setting When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode.
Pin Name RESET
VPP A0-A14 D0-D7 CE OE PGM VDD VSS
Input Input Input/output Input Input Input -- --
PROM programming mode setting and high-voltage applied during program write/verification. Address bus Data bus PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input in PROM programming mode. Positive power supply Ground potential
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1.
Table 2-1. Type of Input/Output Circuit of Each Pin
Pin Name P00 P01/INTP1 P02/INTP2 P03/INTP3 P10/ANI0-P17/ANI7 P30-P32 P33, P34 P35/PCL P36/BUZ P37 P50-P57 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P100/TI5/TO5 P101/TI6/TO6 RESET AVREF AVDD AVSS VPP NC 2 - Input - Connect to VSS. Connect to VDD. Connect to VSS. Connect directly to VSS. Connect to VSS (can leave open) - 5-A 8-A 5-A 8-A 8-A 11 5-A 8-A 5-A Input/Output Independently connect to VDD or VSS via a resistor. 2 8-A Input/Output Circuit Type Input Input/Output Connect to VSS. Independently connect to VSS via a resistor. Input/Output Recommended Connection for Unused Pins
16
PD78P083
Figure 2-1. Types of Pin Input/Output Circuits
Type 2 Type 8-A VDD
pull-up enable IN data VDD P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics output disable N-ch
Type 5-A pull-up enable VDD data
VDD
Type 11 pull-up enable
VDD
P-ch
P-ch VDD P-ch IN/OUT
data
P-ch IN/OUT output disable P-ch N-ch Comparator + - N-ch VREF (threshold voltage) input enable N-ch
output disable
input enable
17
PD78P083
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This is a register to disable use of part of internal memories by software. By setting this internal memory size switching register (IMS), it is possible to get the same memory mapping as that of the mask ROM versions with a different internal memory (ROM, RAM). IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to 46H.
Figure 3-1. Internal Memory Size Switching Register Format
Symbol IMS 7 RAM2 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H After Reset 46H R/W R/W
ROM3 ROM2 ROM1 ROM0 0 0 0 0 1 1 1 0 1 0 0 0
Selection of Internal ROM Capacity 8 Kbytes 16 Kbytes 24 Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection of Internal High-Speed RAM Capacity 512 bytes 384 bytes 256 bytes Setting prohibited
0 0 1
1 1 0
0 1 0
Other than above
Table 3-1 shows the setting values of IMS which make the memory mapping the same as that of the mask ROM version.
Table 3-1. Internal Memory Size Switching Register Setting Values
Target Mask ROM Versions PD78081 PD78082 82H 64H IMS Setting Value
18
PD78P083
4. PROM PROGRAMMING
The PD78P083 has an internal 24-Kbyte PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to "PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode." Caution Programs must be written in addresses 0000H to 5FFFH (The last address 5FFFH must be specified). They cannot be written by a PROM programmer which cannot specify the write address. 4.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 4-1 when the CE, OE, and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 4-1. Operating Modes of PROM Programming
Pin Operating Mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disable Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET VPP VDD CE OE PGM D0 to D7
x : L or H
19
PD78P083
(1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple PD78P083s are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, X times (X 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X times (X 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0-D7 pins of multiple PD78P083s are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high.
20
PD78P083
4.2
PROM Write Procedure
Figure 4-1. Page Program Mode Flow Chart
Start Address = G VDD = +6.5 V, VPP = +12.5 V
X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X = 10 ? Yes
X=X+1 0.1-ms program pulse
Verify 4 bytes Pass No Address = N ? Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Fail
Pass
Verify all bytes All Pass Write end
Fail
Defective product
G = Start address N = Program last address
21
PD78P083
Figure 4-2. Page Program Mode Timing
Page Data Latch Page Program Program Verify
A2-A14
A0, A1
D0-D7 Data Input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL Data Output
VIH PGM VIL VIH OE VIL
22
PD78P083
Figure 4-3. Byte Program Mode Flow Chart
Start Address = G VDD = +6.5 V, VPP = +12.5 V
X=0
X=X+1 0.1-ms program pulse Address = Address + 1 Fail Verify Pass No Address = N ? Yes
VDD = 4.5 to 5.5 V, VPP = VDD
No X = 10 ? Yes
Pass
Verify all bytes All Pass Write end
Fail
Defective product
G = Start address N = Program last address
23
PD78P083
Figure 4-4. Byte Program Mode Timing
Program
Program Verify
A0-A14
D0-D7
Data Input
Data Output
VPP VPP VDD
VDD
VDD + 1.5 VDD VIH
CE VIL VIH PGM VIL VIH OE VIL
Cautions 1. 2. 3.
VDD should be applied before VPP and removed after VPP. VPP must not exceed +13.5 V including overshoot. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP.
24
PD78P083
4.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0-D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in "PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode". (2) Supply +5 V to the VDD and VPP pins. (3) Input address of read data into the A0-A16 pins. (4) Read mode (5) Output data to D0-D7 pins. The timings of the above steps (2) to (5) are shown in Figure 4-5.
Figure 4-5. PROM Read Timings
A0-A14
Address Input
CE (Input)
OE (Input)
D0-D7
Hi-Z
Data Output
Hi-Z
25
PD78P083
*
5. PROGRAM ERASURE (PD78P083DU ONLY)
The PD78P083DU is capable of erasing (FFH) the data written in a program memory and rewriting. To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the programmed data is as follows: * UV intensity x erasing time : 30 W*s/cm2 or more
* Erasure time: 40 min. or more (When a UV lamp of 12,000 W/cm2 is used. However, a longer time may be needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.) When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
6. OPAQUE FILM ON ERASURE WINDOW (PD78P083DU ONLY)
To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when EPROM contents erasure is not performed.
7. ONE-TIME PROM VERSION SCREENING
The one-time PROM version (PD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the condition below.
Storage Temperature 125C Storage Time 24 hours
*
NEC offers for an additional fee one-time PROM writing to marking, screening, and verify for products designated as "QTOP Microcontroller". Please contact an NEC sales representative for details.
26
PD78P083
8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVDD AVREF AVSS Input voltage Output voltage Analog input voltage Output current, high VI1 VI2 VO VAN IOH P10-P17 Per pin Total for P10-P17, P50-P54, P70-P72, P100, P101 Total for P01-P03, P30-P37, P55-P57 Output current, low IOL
Note
*
Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Unit V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA C C
Test Conditions
A9
PROM programming mode -0.3 to +13.5
-0.3 to VDD + 0.3 Analog input pins AVSS - 0.3 to AVREF + 0.3 -10 -15 -15 15 70 70 20 20 -40 to +85 -65 to +150
Per pin Total for P50-P54 Total for P55-P57 Total for P10-P17, P70-P72, P100, P101 Total for P01-P03, P30-P37
Peak value 30
r.m.s. value
Peak value 100
r.m.s. value
Peak value 100
r.m.s. value
Peak value 50
r.m.s. value
Peak value 50
r.m.s. value
Operating ambient temperature Storage temperature
TA Tstg
Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty Caution If the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. The absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. Be sure to use the product with all the absolute maximum ratings observed. Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
Remark
27
PD78P083
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO Test Conditions f = 1 MHz, Unmeasured pins returned to 0 V. f = 1 MHz, Unmeasured pins returned to 0 V. P01-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101 MIN. TYP. MAX. 15 15 Unit pF pF
Remark
Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Ceramic resonator
C2 C1 VPP X2 X1
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency (fX) Note 1 Oscillation stabilization time
Note 2
VDD = Oscillation voltage range After VDD came to MIN. of oscillation voltage range
1.0
5.0
MHz
4
ms
Crystal resonator
VPP X2
X1
Oscillation frequency (fX)
Note 1
1.0
5.0
MHz
C2
C1
Oscillation stabilization time
Note 2
VDD = 4.5 to 5.5 V
10 30 1.0 5.0
ms
External clock
X2
X1
X1 input frequency (fX) Note 1
MHz
PD74HCU04
X1 input high- and low-level widths (tXH, tXL)
85
500
ns
Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after a reset or the STOP mode has been released. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring over other signal lines. * Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit.
28
PD78P083
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 Test Conditions P10-P17, P30-P32, P35-P37, P50-P57, P71 VIH2 P00-P03, P33, P34, P70, P72, P100, P101, RESET VIH3 Input voltage, low VIL1 X1, X2 P10-P17, P30-P32, P35-P37, P50-P57, P71 VIL2 P00-P03, P33, P34, P70, P72, P100, P101, RESET VIL3 Output voltage, high Output voltage, low VOH VOL X1, X2 VDD = 2.7 to 5.5 V 0 0 0 VDD = 4.5 to 5.5 V, IOH = -1 mA IOH = -100 A P50-P57 VDD = 2.0 to 4.5 V, IOL = 10 mA VDD = 4.5 to 5.5 V, IOL = 15 mA P01-P03, P10-P17, P30-P37, P70-P72, P100, P101 Input-leak current, high ILIH1 VIN = VDD VDD = 4.5 to 5.5 V, IOL = 1.6 mA IOL = 400 A P00-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101, RESET ILIH2 Input-leak current, low ILIL1 VIN = 0 V X1, X2 P00-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101, RESET ILIL2 Output leak current, high Output leak current, low Software pull-up resistor ILOH ILOL R VOUT = VDD VOUT = 0 V VIN = 0 V P01-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101 15 40 X1, X2 -20 3 -3 90 A A A k 20 -3 A A 0.5 3 V A 0.4 V 0.4 2.0 V VDD-1.0 VDD-0.5 0.8 0.15VDD 0.4 0.2 V V V V V V VDD = 2.7 to 5.5 V 0 0 0.2VDD 0.2VDD V V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 0.85VDD VDD-0.5 VDD-0.2 0 VDD VDD VDD 0.3VDD V V V V VDD = 2.7 to 5.5 V 0.8VDD 0.8VDD VDD VDD V V VDD = 2.7 to 5.5 V MIN. 0.7VDD TYP. MAX. VDD Unit V
Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
29
PD78P083
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Supply current
Note 1
Symbol IDD1
Test Conditions 5.0-MHz crystal oscillation operating mode (fXX = 2.5 MHz) Note 2 5.0-MHz crystal oscillation operating mode (fXX = 5.0 MHz)
Note 3
MIN.
Note 4 Note 5 Note 5 Note 4 Note 5
TYP. 5.4 0.8 0.45 9.5 1.0 1.4 0.5 280 1.6 0.65 0.1 0.05 0.05
MAX. 16.2 2.4 1.35 28.5 3.0 4.2 1.5 840 4.8 1.95 30 10 10
Unit mA mA mA mA mA mA mA A mA mA A A A
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
IDD2
5.0-MHz crystal oscillation HALT mode (fXX = 2.5 MHz)
Note 2
5.0-MHz crystal oscillation HALT mode (fXX = 5.0 MHz) IDD3 STOP mode
Note 3
Notes 1. Not including AVREF, AVDD currents or port currents (including current flowing into internal pull-up resistors). 2. fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H). 3. fXX = fX operation (when oscillation mode selection register (OSMS) is set to 01H). 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when processor clock control register (PCC) is set to 04H). Remark fxx: Main system clock frequency (fx or fx/2) fx: Main system clock oscillation frequency
30
PD78P083
AC Characteristics
(1) Basic Operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) TI5, TI6 input frequency TI5, TI6 input high-/ low-level widths Interrupt input high-/ low-level widths RESET low-level width tTIH, tTIL tINTH, tINTL tRSL VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 4.5 to 5.5 V fTI fXX = fX Note2 VDD = 4.5 to 5.5 V 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V Symbol TCY fXX = fX/2
Note1
Test Conditions VDD = 2.7 to 5.5 V
MIN. 0.8 2.0 0.4 0.8 0 0 100 1.8 10 20 10 20
TYP.
MAX. 64 64 32 32 4 275
Unit s s s s MHz kHz ns s s s s s
Notes 1. When oscillation mode selection register (OSMS) is set to 00H. 2. When OSMS is set to 01H. Remark fxx: Main system clock frequency (fx or fx/2) fx: Main system clock oscillation frequency
TCY vs VDD (Main System Clock fxx = fx/2 Operation)
TCY vs VDD (Main System Clock fxx = fx Operation)
60
60
Cycle Time TCY [ s]
Operation Guaranteed Range 2.0 1.0 0.5 0.4
Cycle Time TCY [ s]
10
10 Operation Guaranteed Range 2.0 1.0 0.5 0.4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]
Power Supply Voltage VDD [V]
31
PD78P083
(2) Serial Interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK2 *** internal clock output)
Parameter SCK2 cycle time Symbol tKCY1 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK2 high-/low-level width SI2 setup time (to SCK2 ) tKH1, tKL1 tSIK1 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI2 hold time (from SCK2 ) SCK2 SO2 output delay time tKSO1 C = 100 pFNote 300 ns tKSI1 VDD = 4.5 to 5.5 V MIN. 800 1600 3200 4800 tKCY1/2-50 tKCY1/2-100 100 150 300 400 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the SCK2, SO2 output line load capacitance. (b) 3-wire serial I/O mode (SCK2 *** external clock input)
Parameter SCK2 cycle time Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK2 high-/low-level width tKH2, tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI2 setup time (to SCK2 ) SI2 hold time (from SCK2 ) SCK2 SO2 output delay time SCK2 rise, fall time tR2, tF2 tKSO2 C = 100 pFNote VDD = 2.0 to 5.5 V 300 500 1000 ns ns ns tKSI2 tSIK2 VDD = 2.0 to 5.5 V MIN. 800 1600 3200 4800 400 800 1600 2400 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the SO2 output line load capacitance.
32
PD78P083
(c)
UART mode (Dedicated baud rate generator output)
Parameter Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. TYP. MAX. 78125 39063 19531 9766 Unit bps bps bps bps
Transfer rate
(d)
UART mode (External clock input)
Parameter Symbol tKCY3 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 400 800 1600 2400 39063 19531 9766 6510 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns bps bps bps bps ns
ASCK cycle time
ASCK high-/low-level width
tKH3, tKL3
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V
Transfer rate
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V
ASCK rise, fall time
tR3, tF3
33
PD78P083
AC Timing Test Point (Excluding X1 Input)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fx tXL tXH VDD - 0.5 V 0.4 V
X1 Input
TI Timing
1/fTI tTIL tTIH
TI5, TI6
34
PD78P083
Serial Transfer Timing 3-wire serial I/O mode:
tKCY1, 2 tKL1, 2 tR2 SCK2 tKH1, 2 tF2
tSIK1, 2
tKSI1, 2
SI2 tKSO1, 2
Input Data
SO2
Output Data
UART mode (external clock input):
tKCY3 tKL3 tR3 ASCK tKH3 tF3
35
PD78P083
A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Total error
Note
Symbol
Test Conditions 2.7 V AVREF AVDD
MIN. 8
TYP. 8
MAX. 8 1.4 200 AVREF AVDD
Unit bit % s s V V k
Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance
tCONV tSAMP VIAN AVREF RAIREF
19.1 12/fxx AVSS 2.7 4 14
Note Excluding quantization error (1/2 LSB). Shown as a percentage of the full scale value. Remark fxx: Main system clock frequency (fx or fx/2) fx: Main system clock oscillation frequency
36
PD78P083
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Release by RESET Release by interrupt VDDDR = 1.8 V 0 2 17/fx
Note
Test Conditions
MIN. 1.8
TYP. 0.1
MAX. 5.5 10
Unit V A s ms ms
Note 212/fxx or 214/fxx-217/fxx can be selected by bit 0-bit 2 (OSTS0-OSTS2) of oscillation stabilization time selection register (OSTS). Remark fxx: Main system clock frequency (fx or fx/2) fx: Main system clock oscillation frequency
Data Retention Timing (STOP mode released by RESET)
Internal reset operation HALT mode STOP mode Data retention mode VDD VDDDR STOP instruction execution RESET tSREL Operating mode
tWAIT
Data Retention Timing (Standby release signal: STOP mode released by interrupt signal)
HALT mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tWAIT tSREL Operating mode
37
PD78P083
Interrupt Input Timing
tINTL INTP1-INTP3 tINTH
RESET Input Timing
tRSL
RESET
38
PD78P083
PROM Programming Characteristics DC Characteristics
(1) PROM Write Mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V)
Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current Symbol SymbolNote VIH VIL VOH VOL ILI VPP VDD IPP IDD VIH VIL VOH VOL ILI VPP VCC IPP ICC PGM = VIL IOH = -1 mA IOL = 1.6 mA 0 VIN VDD -10 12.2 6.25 12.5 6.5 Test Conditions MIN. 0.7VDD 0 VDD - 1.0 0.4 +10 12.8 6.75 50 50 TYP. MAX. VDD 0.3VDD Unit V V V V A V V mA mA
(2) PROM Read Mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V)
Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current Output leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current Symbol SymbolNote VIH VIL VOH1 VOH2 VOL ILI ILO VPP VDD IPP IDD VIH VIL VOH1 VOH2 VOL ILI ILO VPP VCC IPP ICCA1 VPP = VDD CE = VIL, VIN = VIH IOH = -1 mA IOH = -100 A IOL = 1.6 mA 0 VIN VDD 0 VOUT VDD, OE = VIH -10 -10 VDD - 0.6 4.5 VDD 5.0 Test Conditions MIN. 0.7VDD 0 VDD - 1.0 VDD - 0.5 0.4 +10 +10 VDD + 0.6 5.5 100 50 TYP. MAX. VDD 0.3VDD Unit V V V V V A A V V A mA
Note Corresponding PD27C1001A symbol.
39
PD78P083
AC Characteristics
(1) PROM Write Mode (a) Page program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V)
Parameter Address setup time (to OE ) OE setup time CE setup time (to OE ) Address hold time (from OE ) Symbol Symbol Note tAS tOES tCES tAH tAHL tAHV Input data hold time (from OE ) OE Data output float delay time VPP setup time (to OE ) VDD setup time (to OE ) Program pulse width OE pulse width during data latching PGM setup time CE hold time OE hold time tPGMS tCEH tOEH tPGMS tCEH tOEH 2 2 2 s s s tVPS tVDS tPW tLW tVPS tVCS tPW tOE tLW 1 1.0 1.0 0.095 0.1 0.105 1 ms ms ms s s tDH tDF tAS tOES tCES tDS tAH tAHL tAHV tDH tDF Test Conditions MIN. 2 2 2 2 2 2 0 2 0 250 TYP. MAX. Unit s s s s s s s s ns
Input data setup time (to OE ) tDS
OE Valid data delay time tOE
(b) Byte program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V)
Parameter OE set time CE setup time (to PGM ) Address hold time (from OE ) Input data hold time (from PGM ) OE Data output float delay time VPP setup time (to PGM ) VDD setup time (to PGM ) Program pulse width OE hold time tVPS tVDS tPW tOEH tVPS tVCS tPW tOE -- 2 1.0 1.0 0.095 0.1 0.105 1 ms ms ms s s tDF tDF 0 250 ns Symbol Symbol Note tAS tOES tCES tDS tAH tDH tOES tCES tAH tDH Test Conditions MIN. 2 2 2 2 2 2 TYP. MAX. Unit s s s s s s Address setup time (to PGM ) tAS
Input data setup time (to PGM ) tDS
OE Valid data delay time tOE
Note
Corresponding PD27C1001A symbol.
40
PD78P083
(2) PROM Read Mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V)
Parameter Address Data output delay time CE Data output delay time OE Data output delay time OE Data output float delay time Address Data hold time tOH tOH CE = OE = VIL 0 ns tCE tOE tDF tCE tOE tDF OE = VIL CE = VIL CE = VIL 0 800 200 60 ns ns ns Symbol Symbol Note tACC tACC Test Conditions CE = OE = VIL MIN. TYP. MAX. 800 Unit ns
Note Corresponding PD27C1001A symbol. (3) PROM Programming Mode (TA = 25C, VSS = 0 V)
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. 10 TYP. MAX. Unit s
41
PD78P083
PROM Write Mode Timing (page program mode)
Page Data Latch A2-A14 tAS A0, A1 tDS D0-D7 Hi-Z tVPS VPP VPP VDD tVDS VDD+1.5 VDD VDD tCES VIH CE VIL VIH PGM VIL tLW VIH OE VIL tOES tPW tCEH tOEH Data Input tDH Hi-Z tPGMS tOE Output
Data
Page Program
Program Verify
tAHL
tAHV
tDF Hi-Z tAH
42
PD78P083
PROM Write Mode Timing (byte program mode)
Program A0-A14 tAS D0-D7 VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL tOES tOE tCES tPW tVPS Hi-Z tDS Data Input tDH Hi-Z Data Output tAH tDF Hi-Z Program Verify
tVDS
tOEH
Cautions 1. 2. 3.
VDD should be applied before VPP, and removed after VPP. VPP must not exceed +13.5 V including overshoot. Reliability may be adversely affected if removal/reinsertion is performed while + 12.5 V is being applied to VPP.
PROM Read Mode Timing
A0-A14
Effective Address
VIH CE VIL VIH OE VIL tACCNote 1 D0-D7 Hi-Z tOENote 1 tOH Data Output Hi-Z tDFNote 2 tCE
Notes 1. If you want to read within the range of tACC, make the OE input delay time from the fall of CE a maximum of tACC- tOE. 2. tDF is the time from when either OE or CE first reaches VIH.
43
PD78P083
PROM Programming Mode Setting Timing
VDD VDD 0
RESET
VDD VPP 0 tSMA Effective Address
A0-A14
44
PD78P083
9.
PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42 22
1 A
21
K L
I G J H
F C D N
M
B M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1
Remark The shape and material of ES versions are the same as those of mass-produced versions.
45
PD78P083
PD78P083GB-3B4
44 PIN PLASTIC QFP (
10)
A B
33 34
23 22
detail of lead end
C
D
S Q R
44 1
12 11
F G H P
N
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
J I
M
K M L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.60.4 10.00.2 10.00.2 13.60.4 1.0 1.0 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.535 +0.017 -0.016 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.535 +0.017 -0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. P44GB-80-3B4-3
Remark The shape and material of ES versions are the same as those of mass-produced versions.
46
PD78P083
PD78P083GB-3BS-MTX
44 PIN PLASTIC QFP ( 10)
A B
33 34
23 22
detail of lead end
C
D
S R Q
44 1
12 11
F J G H I
M
K P N
NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition.
M
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.20.2 10.00.2 10.00.2 13.20.2 1.0 1.0 0.37 +0.08 -0.07 0.16 0.8 (T.P.) 1.60.2 0.80.2 0.17 +0.06 -0.05 0.10 2.7 0.1250.075 3 +7 -3 3.0 MAX. INCHES 0.520 +0.008 -0.009 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.520 +0.008 -0.009 0.039 0.039 0.015 +0.003 -0.004 0.007 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.007 +0.002 -0.003 0.004 0.106 0.0050.003 3 +7 -3 0.119 MAX. S44GB-80-3BS
Remark The shape and material of ES versions are the same as those of mass-produced versions.
47
PD78P083
42PIN CERAMIC SHRINK DIP (WINDOW) (600 mil)
X 42 22
1 A Z
I
21 K L
G
J
F D
H
NM
B C
Y
M 0~15 P42DW-70-600A
NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N X Y Z
MILLIMETERS 38.25 MAX. 1.345 MAX. 1.778 (T.P.) 0.46 0.05 0.85 MIN. 3.5 0.3 1.02 MIN. 3.026 5.282 MAX. 15.24 (T.P.) 14.99 0.25 0.05 0.25 12.0 6.0 4-R3.0
INCHES 1.506 MAX. 0.053 MAX. 0.07 (T.P.) 0.018 0.002 0.033 MIN. 0.138 0.012 0.040 MIN. 0.119 0.208 MAX. 0.600 (T.P.) 0.590 0.010 -0.003 0.01 0.472 0.236 4-R0.118
+0.002
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PD78P083
10. RECOMMENDED SOLDERING CONDITIONS
It is recommended that the PD78P083 be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative.
*
Table 10-1. Soldering Conditions for Surface Mount Types PD78P083GB-3B4 : 44-pin plastic QFP (10 x 10 mm) PD78P083GB-3BS-MTX : 44-pin plastic QFP (10 x 10 mm)
Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or less (at 210C or higher), Number of reflow processes: 2 or less < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Package peak temperature: 215C, Reflow time: 40 seconds or less (at 200C or higher), Number of reflow processes: 2 or less < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Solder temperature: 260C or below, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C or below, Flow time: 3 seconds or less (per pin row) IR35-00-2 Symbol
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
--
Caution
Do not use different soldering methods together (except for partial heating method).
Table 10-2. Soldering Condition for Hole-Through Types PD78P083CU : 42-pin plastic shrink DIP (600 mil) PD78P083DU : 42-pin ceramic shrink DIP (with window) (600 mil)
Soldering Method Wave Soldering (only pins) Partial heating Soldering Conditions Solder temperature: 260C or below, Flow time: 10 seconds or less Pin temperature: 300C or below, Flow time: 3 seconds or less (per pin)
Caution
Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with the package.
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PD78P083
*
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available to support development of systems using the PD78P083. Language Processing Software
RA78K/0 CC78K/0 DF78083
Notes 1, 2, 3, 4 Notes 1, 2, 3, 4 Notes 1, 2, 3, 4 Notes 1, 2, 3, 4
Assembler package common to the 78K/0 series C compiler package common to the 78K/0 series Device file used for the PD78083 subseries C compiler library source file common to the 78K/0 series
CC78K/0-L
PROM Writing Tools
PG-1500 PA-78P083CU PA-78P083GB PG-1500 Controller
Notes 1, 2
PROM programmer Programmer adapter connected to the PG-1500 Control program for the PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A
Note 8
In-circuit emulator common to the 78K/0 series In-circuit emulator common to the 78K/0 series (for integrated debugger) Break board common to the 78K/0 series Emulation board common to the PD78078 subseries Emulation probe for the PD78083 subseries Socket mounted on the target system board prepared for 44-pin plastic QFP System simulator common to the 78K/0 series Integrated debugger for IE-78000-R-A Screen debugger for the IE-78000-R Device file used for the PD78083 subseries
IE-78000-R-BK IE-78078-R-EM EP-78083CU-R EP-78083GB-R EV-9200G-44 SM78K0 ID78K0 SD78K/0 DF78083
Notes 5, 6, 7 Notes 4, 5, 6, 7, 8 Notes 1, 2 Notes 1, 2, 5, 6, 7
Notes 1. Based on PC-9800 series (MS-DOSTM) 2. Based on IBM PC/ATTM and its compatibles (PC DOSTM/IBM DOSTM/MS-DOS) 3. Based on HP9000 series 300TM (HP-UXTM) 4. 5. 6. 7. Based on HP9000 series 700TM (HP-UX), SPARCstationTM (SunOSTM), and EWS4800 series (EWS-UX/V) Based on PC-9800 series (MS-DOS + WindowsTM) IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) Based on NEWSTM (NEWS-OSTM)
8. Under development Remarks 1. 2. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 in combination with the DF78083.
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PD78P083
Fuzzy Inference Development Support System
FE9000 FT9080 FI78K0 FD78K0
Note 1 Note 1
/FE9200
Note 2 Note 3
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
/FT9085
Notes 1, 3 Notes 1, 3
Notes 1. Based on PC-9800 series (MS-DOS) 2. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS+Windows) 3. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) Remark Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools.
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PD78P083
*
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name PD78083 Subseries User's Manual 78K/0 Series User's Manual--Instructions 78K/0 Series Instruction Table 78K/0 Series Instruction Set PD78083 Subseries Special Function Register Table 78K/0 Series Application Note Basic (III) IEU-886 IEU-849 U10903J U10904J IEM-5599 IEA-767 Document No. Japanese English IEU-1407 IEU-1372 -- -- -- U10182E
Documents Related to Development Tools (User's Manual)
Document Name RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler CC78K/0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller IBM PC Series (PC DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78078-R-EM EP-78083 SM78K0 System Simulator SM78K Series System Simulator Reference Third party's user open interface specifications SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based Introduction Reference Introduction Reference EEU-852 U10952J EEU-5024 EEU-993 -- -- EEU-1414 EEU-1413 Operation Language Programming know-how EEU-777 EEU-651 EEU-704 EEU-5008 EEU-810 U10057J EEU-867 U10775J EEU-5003 EEU-5002 U10092J -- EEU-1335 EEU-1291 U10540E EEU-1398 U10057E EEU-1427 EEU-1504 EEU-1529 U10181E U10092E Operation Language Document No. Japanese EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEA-618 English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEA-1208
Caution
The contents of the documents listed above are subject to change without prior notice. Make sure to use the latest edition when starting design.
52
PD78P083
Documents Related to Embedded Software (User's Manual)
Document Name 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Basic Document No. Japanese EEU-5010 EEU-829 EEU-862 EEU-858 EEU-921 -- EEU-1438 EEU-1444 EEU-1441 EEU-1458 English
Other Documents
Document Name Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semicoductor Devices Microcontroller-Related Product Guide - Third Party Products - IEI-635 C10535J IEI-620 C10983J MEM-539 MEI-603 MEI-604 Document No. Japanese English IEI-1213 C10535E IEI-1209 C10983E IEI-1201 MEI-1202 --
Caution
The contents of the documents listed above are subject to change without prior notice. Be sure to use the latest edition when starting design.
53
PD78P083
[MEMO]
54
PD78P083
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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PD78P083
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representive. License not needed : PD78P083DU
The customer must judge the need for license : PD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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